Quad-Level Cell NAND Design and Soft-Bit Generation for Low-Density Parity-Check

本文刊于:《Wuhan University Journal of Natural Sciences》 2018年第1期

QLC(Quad-Level Cell) NAND;error-correcti

QLC(Quad-Level Cell) NAND;error-correcting code(ECC);Low-Density Parity-Check(LDPC);Soft-Bit Generation
     QLC(Quad-Level Cell) NAND flash will be one of the future technologies for next generation memory chip after three-dimensional(3 D) TLC(Triple-Level Cell) stacked NAND flash. In QLC device, data errors will easily occur because of 24 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on "half-change" Gray coding are researched. Because of the probable error impact of QLC NAND cell’s voltage change, the solution of generating the soft information after XOR(exclusive OR) the soft bits by internal read mechanism is presented for Low-Density Parity-Check(LDPC) Belief Propagation(BP) decoding in QLC design for its system level application.


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